1. Field of the Invention
The present invention relates to the field of computer systems. More specifically, the present invention relates to registers and execution units of processors of computer systems.
2. Background Information
In copending U.S. Pat. application, Ser. No.: 08/401,411, still pending, filed Mar. 9, 1995, a processor having a scalable, uni/multi-dimensional, virtually/physically addressed operand register file is disclosed. Various upward compatible embodiments, scaled to various performance design points suitable for multi-scalar, vector, and/or multi-processing as well as software pipelined load, calculate, and store processing, can be created for the disclosed processor. Software pipelined load, calculate, and store processing is particularly useful for real-time and/or digital signal processing (DSP) applications.
Real-time/DSP systems are also characterized by the requirement of having to respond to asynchronous events frequently and quickly. The execution model of a real-time/DSP system is based upon a task executing in the foreground (FG), while other tasks are executing in the background (BG). When one of these BG tasks completes, an interrupt request is generated in which the processor is asked to execute a series of instructions that may be completely unrelated to the current task at hand. Typically, the series of instructions to be executed is relatively short. For each of these requests, a processor particularly suited for real-time/DSP applications must be able to respond quickly, perform the required task, and then swiftly resume the interrupted task at the point that it had left off.
Servicing of an interrupt will typically require allocation and storage of local variables by the interrupt service routine (ISR). Conventional approaches to servicing interrupts typically require the ISR to use the same general purpose operand registers used by the executing FG/BG tasks. Thus, for each interrupt, before a subset of the operand registers can be used by the ISR, the content of the operand registers must be saved, and upon servicing the interrupt, their saved contents must be restored. For multi-processing systems, where registers are associated with executing contexts, certain status information of the interrupted context must also be saved before execution control can be transferred to the ISR, and restored upon returning from the ISR. Therefore, it would be desirable if a more efficient approach can be provided to the processor disclosed in the copending application for servicing the frequent and typically short interrupts of real-time/DSP applications.
Likewise, real-time/DSP applications are also characterized by the requirement of having to respond to execution exceptions quickly. Servicing execution exceptions has virtually all the characteristics and requirements of servicing interrupts. Many exceptions raised during execution of real-time/DSP applications can be remedied with a relatively small number of instructions also. Conventional approaches typically service exceptions in the manner interrupts are serviced, thus suffering the same disadvantages described earlier. Therefore, it would be desirable if a more efficient approach can also be provided to the processor disclosed in the copending application for servicing the relatively short exception processing of real-time/DSP applications.
Many complex real-time/DSP applications are further characterized by processing of large data sets. Thus, vector processors are often employed for these applications. However, there is still a significant amount of companion scalar processing that must be performed. Conventional vector processors typically make little provision for supporting scalar processing, thus causing scalar processing and the switching between scalar and vector processing to be performed inefficiently. Therefore, it would be desirable if a more efficient approach can be provided to the processor disclosed in the copending application for performing the companion scalar processing of vectorized real-time/DSP applications.
Many complex real-time/DSP applications are further characterized by the complexity of the operations they perform, such as calculating the COSINE and SINE of various variables, as well as the frequency of the operations they perform, such as performing Fast Fourier Transforms. Typically, these calculations are performed using software library routines. Similar to servicing interrupts/exceptions, conventional approaches also require the software library routines to use the same general purpose operand registers used by the executing FG/BG tasks, thus suffering the same disadvantages described earlier. Furthermore, it would be desirable if native hardware support can be provided for these complex and frequent operations in the higher end models of the performance spectrum. Unfortunately, in order to maintain compatibility, prior art architectures typically do not allow the high end models to do so without also burdening the lower end models to provide the same. Therefore, it would be desirable if a more efficient and scalable approach can be used to allow the processor disclosed in the copending application to provide native hardware support for these complex and frequent operations of real-time/DSP applications.
Lastly, like other applications, real-time/DSP applications can also benefit from the ability of emulating instructions of other architectures as new technology emerges, to preserve the large amount of user investment in their existing real-time/DSP code. Conventional processors typically provide no support for emulating instructions of other existing architectures, making it difficult and costly to exploit the new technology. Therefore, it would be further desirable if a more effective approach can be used to allow the processor disclosed in the copending application to emulate instructions of other existing architectures, making it easier to "convert" existing real-time/DSP applications, and allowing the "converted" real-time/DSP applications to exploit the new technologies.
As will be disclosed in more detail below, these and other desirable results are advantageously achieved by the auxiliary operand register file and its complementary arrangements of the present invention for non-disruptively performing adjunct Execution in the processor disclosed in the copending application.